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FEATURES 80 MHz Pipelined Operation 10-Bit D/A Converters RS-343A/RS-170 Compatible Outputs TTL Compatible Inputs +5 V CMOS Monolithic Construction 28-Pin SOIC Package APPLICATIONS High Definition Television (HDTV) High Resolution Color Graphics Digital Radio Modulation CAE/CAD/CAM Applications Image Processing Instrumentation Video Signal Reconstruction Direct Digital Synthesis (DDS) & I/O Modulation Wireless LAN Wireless Local Loop SPEED GRADES 80 MHz 50 MHz 30 MHz GENERAL DESCRIPTION
CLOCK
CMOS 80 MHz, 10-Bit Video DAC ADV7128
FUNCTIONAL BLOCK DIAGRAM
VAA FS ADJUST VREF REFERENCE AMPLIFIER COMP
ADV7128
D0 D9
10
DATA REGISTER
10
DAC
IOUT
GND
The ADV7128 (ADV(R)) is a video speed, digital-to-analog converter on a single monolithic chip. It consists of a high speed, 10-bit, video D/A converters; a standard TTL input interface; and a high impedance, analog output, current source. The ADV7128 has a 10-bit pixel input port. A single +5 V power supply, an external 1.23 V reference and pixel clock input are and all that are required to make the part operational. The ADV7128 is capable of generating video output signals which are compatible with RS-343A, RS-170 and most proposed production system HDTV video standards, including SMPTE 240M. The ADV7128 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7128 is available in a 28lead small outline IC (SOIC).
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz. 2. Guaranteed monotonic to 10 bits. Ten bits of resolution allows for implementation of linearization functions such as gamma correction and contrast enhancement. 3. Compatible with a wide variety of high resolution color graphics systems including RS-343A/RS-170 and the proposed SMPTE 240M standard for HDTV. 4. Combined with a numerically controlled oscillator (AD9955), it forms a complete frequency synthesizer (DDS). 5. Using the parts reduced power output DAC modes, it is ideal for power and cost sensitive communications type applications.
ADV is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
= +5 V 5%; = 37.5 , C = ADV7128-SPECIFICATIONS (V specifications T V to=T +1.235 V; Rotherwise noted.) 10 pF; R All unless
AA REF L L MIN 1 MAX
SET
= 560
.
Parameter STATIC PERFORMANCE Resolution Accuracy Integral Nonlinearity, INL Differential Nonlinearity, DNL Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 ANALOG OUTPUT Gray Scale Current Range Output Current White Level Black Level LSB Size Output Compliance, VOC Output Impedance, ROUT2 Output Capacitance, COUT2 VOLTAGE REFERENCE Voltage Reference Range, V REF Input Current, IVREF POWER REQUIREMENTS VAA IAA Power Supply Rejection Ratio 2 Power Dissipation DYNAMIC PERFORMANCE Glitch Impulse2, 3 DAC Noise2, 3, 4
K Version 10 1 1 5
Units Bits LSB max LSB max % Gray Scale max Binary V min V max A max pF max mA min mA max mA min mA max A min A max A typ V min V max k typ pF max V min/V max mA typ V nom mA max mA max %/% max mW max mW max pV secs typ pV secs typ
Test Conditions/Comments
Guaranteed Monotonic Max Gray Scale Current = (VREF* 7,969/RSET) mA
2 0.8 1 10 15 22 16.74 18.50 0 50 17.28 0 +1.4 100 30 1.14/1.26 -5 5 125 100 0.5 625 500 50 200
VIN = 0.4 V or 2.4 V
Typically 17.62 mA Typically 5 A
IOUT = 0 mA VREF = 1.235 V for Specified Performance
Typically 80 mA: 80 MHz Parts Typically 70 mA: 50 MHz & 35 MHz Parts Typically 0.12%/%: f = 1 kHz, COMP = 0.1 F Typically 400 mW: 80 MHz Parts Typically 350 mW: 50 MHz & 30 MHz Parts
NOTES 1 Temperature range (T MIN to TMAX); 0C to +70C. 2 Sample tested at +25C to ensure compliance. 3 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 4 This includes effects due to clock and data feedthrough. Specifications subject to change without notice.
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ADV7128 TIMING CHARACTERISTICS1
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t 83 80 MHz Version 80 3 2 12.5 4 4 30 20 3 12
(VAA = +5 V 5%; VREF = +1.235 V; RL = 37.5 , CL = 10 pF; RSET = 560 All specifications TMIN to TMAX2 unless otherwise noted.)
30 MHz Version 30 8 2 33.3 9 9 30 20 3 15 Units MHz max ns min ns min ns min ns min ns min ns max ns typ ns max ns typ
.
50 MHz Version 50 6 2 20 7 7 30 20 3 15
Conditions/Comments Clock Rate Data & Control Setup Time Data & Control Hold Time Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time Analog Output Delay Analog Output Rise/Fall Time Analog Output Transition Time
NOTES 1 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 2 Temperature range (T MIN to TMAX): 0C to +70C 3 Sample tested at +25C to ensure compliance. Specifications subject to change without notice.
t4 t5
CLOCK
t3 t1
DIGITAL INPUTS D0-D9 DATA
t2
t6
t8
ANALOG OUTPUTS (I OUT ) NOTES
t7
1. OUTPUT DELAY ( t6 ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF THE CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. TRANSITION TIME ( t8 ) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. 3. OUTPUT RISE/FALL TIME ( t7 ) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
Figure 1. Video Input/Output Timing
RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage Symbol VAA TA RL VREF Min 4.75 0 1.14 37.5 1.235 Typ 5.00 Max 5.25 +70 1.26 Units Volts C Volts Model Speed ORDERING GUIDE Accuracy Temperature DNL INL Range 1 1 1 0C to +70C 0C to +70C 0C to +70C Package Option* R-28 R-28 R-28
ADV7128KR80 80 MHz 1 ADV7128KR50 50 MHz 1 ADV7128KR30 30 MHz 1
*R = SOIC.
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ADV7128
ABSOLUTE MAXIMUM RATINGS * PIN CONFIGURATION
VAA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VAA VAA VAA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VAA 27 VAA
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V Voltage on Any Digital Pin . . . . . . GND -0.5 V to VAA +0.5 V Ambient Operating Temperature (TA) . . . . . . . . 0C to +70C Storage Temperature (TS) . . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300C Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . . . +220C IOUT to GND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES * Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
26 VAA 25 RSET 24 VREF
23 COMP
ADV7128
TOP VIEW (Not to Scale)
22 VAA 21 IOUT 20 VAA
19 GND 18 GND
17 CLOCK 16 VAA
15 VAA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7128 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN FUNCTION DESCRIPTION
WARNING!
ESD SENSITIVE DEVICE
Pin Mnemonic CLOCK
Function Clock input (TTL compatible). The rising edge of CLOCK latches the R0-R9, G0-G9, B0-B9, SYNC and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Data inputs (TTL compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit. Unused data inputs should be connected to either the regular PCB power or ground plane. Current output. This high impedance current source is capable of directly driving a doubly terminated 75 coaxial cable. Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOUT is given by: IOUT (mA) = 7,969 VREF(V)/RSET() Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 F ceramic capacitor must be connected between COMP and VAA. Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 F decoupling ceramic capacitor should be connected between VREF and VAA. Analog power supply (5 V 5%). All VAA pins on the ADV7128 must be connected. Ground. All GND pins must be connected.
D0-D9 IOUT RSET
COMP VREF
VAA GND
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ADV7128
TERMINOLOGY Color Video (RGB) Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color.
Gray Scale
The maximum positive polarity amplitude of the video signal.
Video Signal
The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256.
Raster Scan
That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be visually observed.
The most basic method of sweeping a CRT one line at a time to generate and display images. If we, therefore, have a graphics system with a 1024 x 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then: Dot Rate = 1024 x 1024 x 60/0.8 = 78.6 MHz The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV7128 on the rising edge of CLOCK, as previously described in the "Digital Inputs" section. It is recommended that the CLOCK input to the ADV7128 be driven by a TTL buffer (e.g., 74F244).
IOUT
DATA
CIRCUIT DESCRIPTION AND OPERATION
The ADV7128 contains one 10-bit D/A converter, with one input channel containing a 10-bit register. Also integrated on board the part is a reference amplifier.
Digital Inputs
Ten bits of data (color information) D0-D9 are latched into the device on the rising edge of each clock cycle. This data is presented to the 10-bit DAC and is then converted to an analog output waveform. See Figure 2.
CLOCK
DIGITAL INPUTS D0-D9
mA 17.61
V 0.66 WHITE LEVEL
ANALOG OUTPUTS IOUT
100 IRE
Figure 2. Video Data Input/Output
0 NOTES
0
BLACK LEVEL
All these digital inputs are specified to accept TTL logic levels.
Clock Input
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75 LOAD.
The CLOCK input of the ADV7128 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and hence the required CLOCK frequency, will be determined by the on-screen resolution, according to the following equation: Dot Rate = (Horiz Res) x (Vert Res) x (Refresh Rate)/ (Retrace Factor) Horiz Res Vert Res Refresh Rate = = = Number of Pixels/Line. Number of Lines/Frame. Horizontal Scan Rate. This is the rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system. Total Blank Time Factor. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8).
2. V REF = 1.235V, R SET = 560. 3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. IOUT Video Output Waveform
Table I. Video Output Truth Table for the ADV7128
Description WHITE LEVEL VIDEO VIDEO to BLACK BLACK LEVEL
IOUT1 17.62 video video 0
DAC Input Data 3FF data data 00H
NOTE 1 Typical with full scale = 17.62 mA. V REF = 1.235 V, R SET = 560 .
Retrace Factor =
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ADV7128
Reference Input
An external 1.23 V voltage reference is required to drive the ADV7128. The AD589 from Analog Devices is an ideal choice of reference. It is a two-terminal, low cost, temperature compensated bandgap voltage reference which provides a fixed 1.23 V output voltage for input currents between 50 A and 5 mA. Figure 4 shows a typical reference circuit connection diagram. The voltage reference gets its current drive from the ADV7128's VAA through an on-board 1 k resistor to the VREF pin. A 0.1 F ceramic capacitor is required between the COMP pin and VAA. This is necessary so as to provide compensation for the internal reference amplifier. A resistance RSET connected between RSET and GND determines the amplitude of the output video level according to the following equation: IOUT (mA) = 7,969 x VREF(V)/RSET() (1) Using a variable value of RSET, as shown in Figure 4, allows for accurate adjustment of the analog output video levels. Use of a fixed 560 RSET resistor yields the analog output levels as quoted in the specification page. These values typically correspond to the RS-343A video waveform values as shown in Figure 3.
ANALOG POWER PLANE 0.01F COMP VAA +5V
will develop RS-343A video output voltage levels across a 75 monitor.
IOUT DAC (CABLE) ZS = 75 (SOURCE TERMINATION) ZL = 75 (MONITOR) ZO = 75
Figure 5a. Analog Output Termination for RS-343A
A suggested method of driving RS-170 video levels into a 75 monitor is shown in Figure 5b. The output current level of the DAC remains unchanged, but the source termination resistance, ZS, on the DAC is increased from 75 to 150 .
IOUT DAC ZO = 75 (CABLE)
ZS = 150 (SOURCE TERMINATION)
ZL = 75 (MONITOR)
Figure 5b. Analog Output Termination for RS-170
I REF ~ 5mA
1k VREF TO DAC RSET
More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in an Application Note entitled "Video Formats & Required Load Terminations" available from Analog Devices, publication no. E1228-15-1/89.
AD589 (1.235V VOLTAGE REFERENCE)
500 R SET 560 GND 100
Figure 3 shows the video waveforms associated with the current output driving the doubly terminated 75 load of Figure 5a.
Gray Scale Operation
ADV7128
The ADV7128 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel used for video information).
Video Output Buffer
*ADDITIONAL CIRCUITRY, INCLUDING DECOUPLING COMPONENTS, EXCLUDED FOR CLARITY
Figure 4. Reference Circuit
D/A Converter
The ADV7128 contains a 10-bit D/A converter. The DAC is designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = "1") or GND (bit = "0") by a sophisticated decoding scheme. The use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations.
Analog Output
The ADV7128 is specified to drive transmission line loads, which is what most monitors are rated as. The analog output configurations to drive such loads are described in the Analog Interface section and illustrated in Figure 5. However, in some applications it may be required to drive long "transmission line" cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between 2 and 4 will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applications. These include the AD84x series of monolithic op amps. In very high frequency applications (80 MHz), the AD9617 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit will result in any desired video level. -6- REV. 0
The analog output of the ADV7128 is a high impedance current source. The current output is capable of directly driving a 37.5 load, such as a doubly terminated 75 coaxial cable. Figure 5a shows the required configuration for the output connected into a doubly terminated 75 load. This arrangement
ADV7128
Z2 Z1 +VS 0.1F
The analog ground plane should encompass all ADV7128 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers.
Z O = 75 (CABLE) ZL= 75 (MONITOR)
2 IOUT DAC 3
7
75 6 0.1F
AD848
4
The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7128.
Power Planes
ZS = 75 (SOURCE TERMINATION)
-V S GAIN (G) = 1+ Z1 Z2
Figure 6. AD848 As an Output Buffer
PC Board Layout Considerations
The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV7128 (VAA) and all associated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 7. This bead should be located within three inches of the ADV7128. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7128 power pins, voltage reference circuitry and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling.
Supply Decoupling
The ADV7128 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7128 it is imperative that great care be given to the PC board layout. Figure 7 shows a recommended connection diagram for the ADV7128. The layout should be optimized for lowest noise on the ADV7128 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should be minimized so as to minimize inductive ringing.
Ground Planes
Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (See Figure 7.) Optimum performance is achieved by the use of 0.1 F ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.
The ADV7128 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 7. This bead should be located as close as possible (within 3 inches) to the ADV7128.
COMP C6 0.1F VIDEO DATA INPUTS D0 D9 C3 0.1F VREF C4 0.1F C5 0.1F C2 10F L1 (FERRITE BEAD) +5V (VCC ) C1 33F VAA ANALOG POWER PLANE
ADV7128
GND R SET 560 RSET R1 75
Z1 (AD589) ANALOG GROUND PLANE
GROUND L2 (FERRITE BEAD) COMPONENT C1 C2 VIDEO OUTPUT C3, C4, C5,C6 L1, L2 R1 R SET Z1 DESCRIPTION 33F TANTALUM CAPACITOR 10F TANTALUM 0.1F CERAMIC CAPACITOR FERRITE BEAD 75 1% METAL FILM RESISTOR FAIR-RITE 274300111 OR MURATA BL01/02/03 DALE CMF-55C VENDOR PART NUMBER
CLOCK IOUT
560 1% METAL FILM RESISTOR DALE CMF-55C 1.235V VOLTAGE REFERENCE ANALOG DEVICES AD589JH
Figure 7. ADV7128 Typical Connection Diagram and Component List
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ADV7128
It is important to note that while the ADV7128 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three terminal voltage regulator.
Digital Signal Interconnect Analog Signal Interconnect
The ADV7128 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 (doubly terminated 75 configuration). This termination resistance should be as close as possible to the ADV7128 so as to minimize reflections. Additional information on PCB design is available in an application note entitled "Design and Layout of a Video Graphics System for Reduced EMI." This application note is available from Analog Devices, publication number E1309-15-10/89.
The digital signal lines to the ADV7128 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7128 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
SOIC (R-28)
28 0.299 (7.60) 0.291 (7.40) PIN 1 1 14 15
0.419 (10.65) 0.394 (10.00)
0.712 (18.10) 0.697 (17.70) 0.104 (2.65) 0.093 (2.35) 0.011 (0.30) 0.004 (0.10) 0.050 (1.27) BSC 0.019 (0.49) 0.014 (0.35) 0.012 (0.32) 0.009 (0.23)
0.05 (1.27) 0.016 (0.40)
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PRINTED IN U.S.A.
C1760-24-1/93

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